Technical SPARC CPU Resources

Bruce Ediger

This page contains my collection of links to information available on-line about the SPARC CPU. Most information about SPARC is fluff: marketing collateral or watered-down pap. I intend this collection to contain useful, technical material.

Compiler Support for Sparc Architecture Processors
Roland G. Ouellette's MS thesis, Department of Computer Science, University of Illinois, Urbana IL, Sept. 1994

Register Windows and User-Space Threads on the SPARC
An examination of SPARC procedure calling conventions, by David Keppel. University of Washington technical report UW-CSE-91-08-01.

Various usenet articles from comp.compilers:
Register window overflow and underflow handling in practice
The stack pointer
Advice on SPARC ABI
SPARC instruction set and compiler writers

Faster Dynamic Linking for SPARC V8 and System V.4
SPARC binary calling conventions with respect to run-time dynamic linking, by David Keppel and Stephen R. Russell. University of Washington calls that paper tech report UW-CSE-93-12-08.

ABSS: SPARC multiprocessor simulator
Web page of a SPARC simulator. Includes source code and a paper describing the simulator.

SPARC International Technical Documents.
You can download SPARC V8 and SPARC V9 Architecture Manuals from these folks. They have SPARC Application Binary Interface specs, too.

ABI Compliance and Global Registers Usage in SPARC[tm] V8 and V9 Architecture
The differences between global register usage in SPARC V8 and V9.

Implementation Characteristics of Current SPARC[tm] V9-Based Product
Compares various implementations of SPARC V9 architecture at the instruction level. The document weighs in at 167 pages, so plenty of detail exists.

Lazy Context Switching Algorithms for Sparc-like Processors
Jochen Liedtke, GMD Technical Report No. 776

Kennedy Mutio of Earlham College teaches CS63 Principles of Computer Organization.
This class apparently includes Research Project: The SPARC Architecture

Specifying Representations of Machine Instructions
by Norman Ramsey of University of Virginia and Mary F. Fernandez of AT&T Labs. Ramsey & Fernandez developed a machine-independent way of specifying the bit-level format of instructions. The paper has a subsection devoted to SPARC instructions.

Principles of Computer Architecture
on-line book project by Miles Murdocca contains some SPARC-related material

Compiler Construction Course Material
by Peter C.J. Graham. The web page possesses course material for University of Manitoba's class 74.429 Compiler Construction. Includes a printable (PostScript) beginner's guide to the SPARC instruction set architecture.

Die SPARC, a german-language overview of the SPARC architecture. Includes a few diagrams that might contain useful information.

A 1998 SunWorld magazine article that describes how the Solaris kernel does mutual exclusion locking on a hardware level.

Numerical Computation Guide - SPARC Behavior and Implementation
The specifics of SPARC floating point co-processors (various SPARC V7 machines) and SPARC floating point implementation (V8 and V9 machines).

CS 341Lab manual
Lab manual for a University of New Mexico class in "Computing Systems", contains a pretty good introduction to SPARC assembly basics.

Understanding SPARC stacks and registers
A big, detailed description of how SPARC register windows interact with function calls and returns.

Sun Microsystem's SPARC Assembly Language Reference Manual. The chapter on Assembler Syntax seems particularly trenchant.

SPARC Architecture, Assembly Language Programming, and C  second edition
by Richard P. Paul. I haven't read the 2nd edition, but the 1st edition concerned itself with beginning programming issues, couched in SPARC assembly language instead of more common "teaching languages" like Pascal or Java. It does cover things that a lot of high-level language books gloss over, like assembly-language-level calling conventions, how stack frame layouts correspond to C variables, and ways to interface between C and assembly. The publishers, Prentice-Hall, put most or all of the exercises on the web.

The LEON SPARC Processor.

LEON is a synthesisable VHDL model of a 32-bit SPARC compatible processor, developed by the European Space Agency (ESA) for future space missions. To promote the SPARC architecture and enable development of system-on-a-chip (SOC) devices using SPARC cores, ESA is making the full source code freely available under the GNU LGPL license.
Holy cow. Looks like you can download VHDL model source code. Someone at University of Toronto has actually had parts made from the LEON design.

SALTO - System for Assembly-Language Transformation and Optimization
A system for profiling and tuning assembly language code on embedded uniprocessors. Said to contain a SPARC v7 machine description.

A note on compiling Scheme to SPARC assembly language, and then assembling it. I think this all gets done in Scheme.

Fujitsu's SPARClite manual, which includes some programming information. Pretty hard core.

Two related links: Least Cost Path Machine Assembler, and Least Cost Path Machine Linker. These constitute a SPARC assembler and and ELF linker, written as some kind of class project. The contain an impressive amount of information, with tons of links worth following.


Tue May 19 10:09:23 MDT 1998 - separated from SPARC assembler paper
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